Data from FPGA to host

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Tell me something I don't know: what need are the constraints? I see that Quartus II is complaining when I don't do that part but why? For me, doing things without any constraint is easier but it wants to be constrained!

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An FPGA design typically requires; HDL code to describe the design, FPGA device and device settings (eg, what to do with unused pins), pinout constraints, and timing constraints.

The first two things are absolutely required. The timing constraints are not required to synthesize a design, but Quartus will complain, because it recognizes that you are using synchronous logic (clocks), but it has no idea how what clock frequency you expect your design to operate at. That is why you have to provide timing constraints.

Cheers,

Dave