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Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it?

For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.