cycloneIII any tutorial how to drive lcd

I guess, all Altera examples for interfacing LCD are based an NIOS embedded processor. I suggest to take the time to study some general literature and tutorials to understand, what's the purspose of NIOS and why basically all ethernet, display, audio or RS232 examples are using it.

However, you have to decide, if it's also meaningful for your intended FPGA application. It's possible as well, to control the LCD in pure HDL code. To my opinion, Altera should have also HDL examples. Otherwise, you're giving the impression, that complex actions necessarily need a processor (which isn't the case, actually). And the user may ask, if he should rather use a fast standard µP than an Altera FPGA...

Any good tutorials that come to mind? I am looking for some.

And yes, why do all the peripherals use Nios? Your points all good FvM. I did have those questions in my head.

Even if I do want to use Nios, how do I call the Nios program so that when the design written in Verilog gives a certain output, the LCD can be instructed to display the related values?

The My First Nios II Software Design tutorial only tells how to write Hello World. I still cannot imagine how to join the pieces, from the verilog programmed into fpga output to the lcd on board.

Any direction to follow up tutorials is appreciated.

Thanks.

Sequential code execution in a processor achieves better utilization of short resources, e.g. when performing complex floating point calculations, string processing or controlling slow sequential processes. Parallel signal processing (the basic capability of FPGA) is superior to handle real time or other fast data streams. Many high performance systems make use of both principles. Software processors (as NIOS II) are combining both in one device.

LCD display control is basically slow and sequential for two reasons:

1. The display has a limited data throughput, requiring delays of several 100 us for some commands.

2. As a human interface, it's update rate is practical limited by the operators perception speed.

For this reason, display control is natural candidate for NIOS II, if it's present in a design. Otherwise, it can be controlled by HDL code, as mentioned before.

Your question, how Verilog design output can directed to the NIOS processor, has many possible answers. If you think of the NIOS as a usual uP and of the HDL part as an intelligent peripheral connected to it, you can imagine similar solutions as known with conventional hardware processors: Command and status registers, register files, dma transfer using a parallel data bus. Your HDL part signals an event, an the NIOS part reacts on it by displaying a message.

Mr FvM, Your answers are very helpful. A helping hand makes a happy heart.

Next question, on the Cyclone III development kit board, the Nios is stated as Soft IP. So when I send a signal from the HDL code part to the Nios,

i.) can both the HDL part and the Nios part be programmed into the same FPGA together?

ii.) In what form does the output from HDL part call the Nios part?

iii.) Is it right that if the Nios is an embedded processor like the one in a Nios Dev Kit (unike the cyclone III I have), then the HDL part will be programmed into the FPGA but the C+ part will reside in the processor.

Thank You.