cycloneIII any tutorial how to drive lcd

Sequential code execution in a processor achieves better utilization of short resources, e.g. when performing complex floating point calculations, string processing or controlling slow sequential processes. Parallel signal processing (the basic capability of FPGA) is superior to handle real time or other fast data streams. Many high performance systems make use of both principles. Software processors (as NIOS II) are combining both in one device.

LCD display control is basically slow and sequential for two reasons:

1. The display has a limited data throughput, requiring delays of several 100 us for some commands.

2. As a human interface, it's update rate is practical limited by the operators perception speed.

For this reason, display control is natural candidate for NIOS II, if it's present in a design. Otherwise, it can be controlled by HDL code, as mentioned before.

Your question, how Verilog design output can directed to the NIOS processor, has many possible answers. If you think of the NIOS as a usual uP and of the HDL part as an intelligent peripheral connected to it, you can imagine similar solutions as known with conventional hardware processors: Command and status registers, register files, dma transfer using a parallel data bus. Your HDL part signals an event, an the NIOS part reacts on it by displaying a message.