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APaci1's avatar
APaci1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

CYCLONE5 SOC - Eth1 timing problems at 1 gbps

HI, I attempts to use my HPS Emac1 port in GMII, connected to micrel PHY. I have a running Angstrom distro, after boot it runs fine at 100 mbps only. At 1Gbps, it depends of compilation! I try many costraints, I create clocks, derive clocks and so on. Nothing. The only thing that allows to run at 1Gbps is if I put a SIGNALTAP to eth tx/rx buses...

Have you meet similar issues?

(obviously I use certified dlink and cat6 cables)

I'm tryng to do something with Timequest... bus speed for 1Gbps in GMII is only 125 Mhz...

why Cyclone5 SoC has this issues without excess speed signals??

I'm attempting to define a common delay for Eth 8wire buses... but timequest fails to read my sdc scripts as follows:

set_input_delay -clock {eth_gtx_clk} 1 [get_ports {eth_rx[0] eth_rx[1] eth_rx[2] eth_rx[3] eth_rx[4] eth_rx[5] eth_rx[6] eth_rx[7]}]

Thanks for any suggestion!

3 Replies

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello,

    May I know how did you connect the MAC to the external PHY? which clock did you use?

  • APaci1's avatar
    APaci1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi Jumah! I connect the 125 Mhz generated from HPS in QSYS, exported to external Micrel PHY.

    This design runs fine at 1 Gb only if I connect a Signal Tap to Ethernet wires (GMII mode) and the eth_gtx_clk. (!!!!)

    If I disable STAP , design runs only at 100 Mbps....

    So I think to timing issue.. I attempt to do all.. I assign fast registers to pin planner, eth_gtx_clock is defined as clock, with 125 Mhz timing and so on.. but nothing to do.

  • APaci1's avatar
    APaci1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Good morning! I restart this activity now! Last attempts is add two little fifos, dual clock, one from hps to phy and vice versa.

    Section from phy is read with hps generated gtx clk, and written with 125 mhz generated from FPGA PLL

    Section to phy is written with hps generated gtx clk, and read with 125 mhz generated from FPGA PLL

    Wrreq and Rdreq are always set to 1

    This should separe two clock domains ..

    I must try this issue, I'll do today I hope...