CYCLONE5 SOC - Eth1 timing problems at 1 gbps

Hi Jumah! I connect the 125 Mhz generated from HPS in QSYS, exported to external Micrel PHY.

This design runs fine at 1 Gb only if I connect a Signal Tap to Ethernet wires (GMII mode) and the eth_gtx_clk. (!!!!)

If I disable STAP , design runs only at 100 Mbps....

So I think to timing issue.. I attempt to do all.. I assign fast registers to pin planner, eth_gtx_clock is defined as clock, with 125 Mhz timing and so on.. but nothing to do.