Forum Discussion
APaci1
Occasional Contributor
Occasional ContributorCYCLONE5 SOC - Eth1 timing problems at 1 gbps
HI, I attempts to use my HPS Emac1 port in GMII, connected to micrel PHY. I have a running Angstrom distro, after boot it runs fine at 100 mbps only. At 1Gbps, it depends of compilation! I try many c...
APaci1Occasional Contributor
Occasional ContributorGood morning! I restart this activity now! Last attempts is add two little fifos, dual clock, one from hps to phy and vice versa.
Section from phy is read with hps generated gtx clk, and written with 125 mhz generated from FPGA PLL
Section to phy is written with hps generated gtx clk, and read with 125 mhz generated from FPGA PLL
Wrreq and Rdreq are always set to 1
This should separe two clock domains ..
I must try this issue, I'll do today I hope...
