CYCLONE5 SOC - Eth1 timing problems at 1 gbps

Good morning! I restart this activity now! Last attempts is add two little fifos, dual clock, one from hps to phy and vice versa.

Section from phy is read with hps generated gtx clk, and written with 125 mhz generated from FPGA PLL

Section to phy is written with hps generated gtx clk, and read with 125 mhz generated from FPGA PLL

Wrreq and Rdreq are always set to 1

This should separe two clock domains ..

I must try this issue, I'll do today I hope...