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Altera_Forum's avatar
Altera_Forum
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9 years ago

Cyclone III Development Board - Video Image Processing Suite - Hardware revisions?

Hi,

I'm using the Cyclone III Development Board and the Video Image Processing Suite for many years.

I use the VIP-reference-design on some boards from the year 2007 a it's working fine.

In the near future I ordered three new boards with hardware from 2011, but te VIP-reference-design isn't working on them.

It works only on the old boards. I cannot see many differences on the boards.

I'm using the orginal .sof from Altera and a self-compiled .sof.

Using the self-compiled .sof I can figure out, that the Nios-programm doesn't start properly.

Nios can program and verify the .elf - but it doesn't start.

Is there a (relevant) change in the harware revision?

Best regards

Mark

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Update:

    The new Cyclone III development boards use new hardware components. The hardware revision didn't change (yet Rev. E).

    The DDR2 changed from Micron MT47H32M16HR-3:F (8 Meg x 16 Bit x 4 banks = 512 Mbit = 64 MB ) to MT47H64M16HR-25E:H (8 Meg x 16 Bit x 8 banks = 1024 Mbit = 128 MB ). The old ones are DDR2-667 (3 ns), the new ones are DDR2-800 (2.5 ns)

    Changing the timing in SOPC-Builder / QSYS and adding an additional bank adress fixed the Problem wit the DDR.

    The SDRAM/UTRAM was a Samsung K1B3216B2E -BI70. The new one is a Micron MT45W2MW16BGB-701 IT.

    The configuration registers are different. So if you are using the SDRAM asynchronously,it works fine. Using Bursts (like the demo-designs) it fails.

    I didn't found a solution for this yet. I don't find a datasheet for the old K1B3216B2E, so I can't change the VHDL-code for the Demonstration/example code.

    Possibly someone else can find a solution.

    Best regards

    Mark
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    solution for the DDR2-RAM (no solution for the utram yet):

    The are two possible solutions for this issue.

    The first solution means compatibility with the old Hardware, the second solution will use the new full memory of DDR2-RAM (bottom and top)

    preparatory work for both solutions:

    Go to pin planner and add the node: "memtop_ba[2]" to PIN_C23, IO-Standard SSTL-18 Class I, 12mA

    Go to pin planner and add the node: "membot_ba[2]" to PIN_AH4, IO-Standard SSTL-18 Class I, 12mA

    First solution (compatibility with old boards)

    -simply tie the new both Pins to ground

    Second solution (use the new more memory)

    -go to QSYS / SOPC-Builder => DDR2 SDRAM Controller with Altmemphy => Memory Settings => modify parameters => bank address width => Change from 2 to 3

    repeat it for both (top and bottom) DDR2

    Best Regards

    Mark