Cyclone III Development Board - Video Image Processing Suite - Hardware revisions?

Update:

The new Cyclone III development boards use new hardware components. The hardware revision didn't change (yet Rev. E).

The DDR2 changed from Micron MT47H32M16HR-3:F (8 Meg x 16 Bit x 4 banks = 512 Mbit = 64 MB ) to MT47H64M16HR-25E:H (8 Meg x 16 Bit x 8 banks = 1024 Mbit = 128 MB ). The old ones are DDR2-667 (3 ns), the new ones are DDR2-800 (2.5 ns)

Changing the timing in SOPC-Builder / QSYS and adding an additional bank adress fixed the Problem wit the DDR.

The SDRAM/UTRAM was a Samsung K1B3216B2E -BI70. The new one is a Micron MT45W2MW16BGB-701 IT.

The configuration registers are different. So if you are using the SDRAM asynchronously,it works fine. Using Bursts (like the demo-designs) it fails.

I didn't found a solution for this yet. I don't find a datasheet for the old K1B3216B2E, so I can't change the VHDL-code for the Demonstration/example code.

Possibly someone else can find a solution.

Best regards

Mark