Can I use GXB PIN of Stratix 10 as a pure data line?

Hello,

Can the GXB pin be used as a pure high speed data line using 28GSPS NRZ without any protocol? for example, I wish to send 010010001010... out from one of the GXB differential pair, and the data code can be controlled by the verilog code.

When I compile the code with quartus, i get the following error info. I seems that i can not assign the GXB pin as a output pin?

Below is my code.

module m28GSPS(clk,rst,test);
input clk,rst;
output reg test;

always @(negedge rst or posedge clk)
begin
if(~rst)
begin
test <= 0;
end
else
begin
test <= 1;
end
end
endmodule

Below is the error

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (0, 31) to (0, 31), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): test
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough differential output pin locations available (1 location affected)
Info (175029): pin containing PIN_D4
Info (175015): The I/O pad test is constrained to the location PIN_D4 due to: User Location Constraints (PIN_D4)
Info (14709): The constrained I/O pad is contained within this pin
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Thanks and best regards,