New Contributor
Regular ContributorHi,
There is a difference in the Cyclone V and Stratix 10 transceiver architectures:
In Cyclone V we cannot bypass the serdes logic whereas in S10 we can. Compare the screen shots below.
S10:
Cyclone V:
So it is not possible to implement what you want to, in Cyclone V.
Regards
New ContributorHi Ash_R_Intel,
I have downloaded V21.2 from intel website, after installing Quartus, it is great to find that the GXB pin can be assigned as high speed differential IO, thank you.
Now I want to know if I can use the GXB pin like nomal LVDS pins with some kind of IPcore, since when I use lvds_tx ipcore, it is able to work no more than 1.4G, but i want to produce 28GSPS plain signal (only 0,1bit, without any kind of coding format,even 8-10 coding or 64-66 coding) with GXB, is there any kind of ipcore to do this job?
