Occasional ContributorBuilding DDR controller Example Design - Component DDR over Agilex board
Hello
I am trying to build a DDR controller example design for DDR component memory using Agilex FPGA board - DK-DEV-AGI027-RA.
- I have already created example design as described using "External Memory Interfaces Intel®
Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide".
- Added pin mapping as per schematic shared over Intel's website.
- Configured power management pin setting and address in Device setting.
- Added timing constraint using sdc file both for PLL ref clock (33.33 MHz) as well as JTAG clock (16MHz) in JTAG sdc template. Timing is also met as verified in timing analyzer.
- Memory clock configured - 1333.33 MHz.
There are no errors or critical warning till SOF file generation.
But when I try to debug using STP (Signal Tap analyzer file) I am getting cal fail issue.
Even when I try to debug using System Console (as recommended the user guide), I am getting below error while Creating Memory Interface Connection.
"master_read_32: This transaction did not complete in 60 seconds. System console is giving up."
"An error occurred while running script"::emif_cal_dbg::top::activate_interface_callback":
Can you suggest where I am going wrong and what could be the possible cause of this error.
regards
Madhur
Hi Madhur,
Please download the DK-DEV-AGI027-RA/RA-B installer package from the devkit website.
The serial number that you have shared is belong to this devkit.
Agilex™ 7 FPGA I-Series Development Kit (Production 2x R-Tile & 1x F-Tile)
(Power Solution 2)
DK-DEV-AGI027-RA AGIB027R29A1E1VB 8100505 Please try to generate the example design based on this devkit and DDR4 setting from this devkit.
Or you can use the existing design in this devkit file.
You also may test the devkit with BTS application but need to use with Quartus version 24.3.1.
From the BTS, you can quick check if there is any error during read and write process of the DDR4 interface.
Regards,
Adzim
