Forum Discussion
Building DDR controller Example Design - Component DDR over Agilex board
- 1 year ago
Hi Madhur,
Please download the DK-DEV-AGI027-RA/RA-B installer package from the devkit website.
DK-DEV-AGI027-RA/RA-B (v24.3.1 or higher)
The serial number that you have shared is belong to this devkit.
Agilex™ 7 FPGA I-Series Development Kit (Production 2x R-Tile & 1x F-Tile)
(Power Solution 2)
DK-DEV-AGI027-RA AGIB027R29A1E1VB 8100505 Please try to generate the example design based on this devkit and DDR4 setting from this devkit.
Or you can use the existing design in this devkit file.
You also may test the devkit with BTS application but need to use with Quartus version 24.3.1.
From the BTS, you can quick check if there is any error during read and write process of the DDR4 interface.
Regards,
Adzim
Hi Madhur,
Which Quartus version that you are currently using?
Have you run the board with example design from the board file?
The design can download from this link: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html
Which DDR4 that you are configuring? Is it DDR4 on Bank 2B, 2C or 3C?
Are you already enable the EMIF Debug Toolkit in EMIF IP?
Regards,
Adzim