Avalon st single clock fifo

The Embedded Peripherals IP user guide has details on the registers:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

Hi Srinivasan,

Did the above reply address your problem? Do you have more questions?

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

Hi,

You can find that information on Table 10 on page 35 of the document sent above.

This design example might help: https://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/rapidio-ii-reference-design-for-avalon-st-pass-through-interface/

Regards,

Nurina

Hi,

Unfortunately we don't have what you want from our example design catalog. Perhaps generating a testbench on Platform Designer could help?

You can also watch this video for reference, it gives detailed explanation on how you can use Avalon-ST.

Let me know if this helps.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.