Forum Discussion

Occasional Contributor

4 years ago

Avalon st single clock fifo

Hi, I am using Avalon st single clock FIFO...In that how to give CSR data and address. Otherwise can anyone share the reference design using CSR in Avalon FIFO...

Nurina

Regular Contributor

4 years ago

Hi,

You can find that information on Table 10 on page 35 of the document sent above.

This design example might help: https://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/rapidio-ii-reference-design-for-avalon-st-pass-through-interface/

Regards,

Nurina

srinivasan

Occasional Contributor

4 years ago

Hi,
Thanks for your reply,
Can you please share the quartus project design file for Avalon st single clock fifo using CSR interface with testbench...

Because I am struggling in giving the CSR address and CSR write data for getting almost empty and almost fill signal...

Can anyone please help me on this

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Avalon st single clock fifo

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