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Altera_Forum
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17 years ago

Audio CODEC AIC23 vhdl/verilog

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any controller or IP for controlling this audio codec. I am just wondering does any of you guys have any Verilog/VHDL example codes to control this audio codec. If you do not have then could you please direct me somewhere from where I will be able to get it. Your help would be highly appreciated. Thanks.

29 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You require SPI/I2C controller to control CODEC and need I2S controller for Audio Interface. You should be able to find SPI controller in SOPC builder. For free Verilog/VHDL code of I2C controller and I2S Controller, you can visit www.opencores.org. And if you planning to FPGA proven controller there are so many IP vendors providing I2S and I2C controller IP core. I guess if you want to buy IPs, you should visit www.slscorp.com for I2C and I2S controller.

    All the best,

    Ketan
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Basically both interfaces are simply shift registers with a bit counter, that controls chip select respectively data latching, additionally a clock divider Just a few lines of HDL code.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for replying. Unfortunately, the I2S is the easy part. It's setting up the

    data frames, which is specific to the AIC23, is most of the work. Does anybody have any example or any IP regarding that ? Thanks for ur help in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi, The attached is a Quartus II project for 2S60 DSP kit. The design includes Verilog codes for AIC23 audio CODEC, which digitize Line-in analog and play back to Line-out.

    The sample is fully controlled by a HDL state machine, but normally I use a Nios II controlled version and it’s much more flexible. If you love Nios II I will attach it.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello EOFZ,

    Thanks a lot for your helpful reply. I really appreciate that. I will try to check this program soon. If I have any question I will ask you then. Could you please attach the NIOS II controlled version also ?

    Thanks again.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Blue Sky,

    My design might not be readable, welcome your comments and questions.

    Perhaps, I can upload Nios II version by next week. This version controls AIC registers in I2C mode using opencores IP.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Blue Sky,

    Please update the aic23_avalon_mm_ctrl.v file as following:

    Replace line# 56:

    if (~wr_n)

    with

    if (~wr_n & ~waitrequest).

    This protect av_data when wr_n assertion comes too early.

    BTW. If you have some about Ethernet, please post on the forum. I have no experience of it and I can not reach you through e-mail…
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I am trying to implement a 32-tap band pass filter using the audio codec. i tried to connect the adc_data to input of the filter and dac_data to output of the filter in top.v. But it is not working.

    Please help me with the protocols between the two modules.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi pluhadia,

    If you post your sample code, you may get helpful advice.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi EOZF, this is the behavioral sample code. It is working in the software simulation but it is not working in real time application.

    coeffs[32] = {,,,}; //32 tap low pass filter coeffs precalculated

    x[32];

    thread {

    input = read input port;

    x[0] = input;

    output = 0;

    for (i=0; i<32; i++)

    {

    output = output + (x*coeff); //convoluting input with filter coeffs

    }

    for (i=32; i>0; i--)

    {

    x[i]=x[i-1]; //need to store 33 samples of input

    }

    write output to output port;

    } //end of thread

    In top.v:

    always @(clk_in_40M) begin

    if(adc_dac_enable) begin

    module_input_port <= adc_data_L;

    end

    end

    always @(clk_in_40M) begin

    if(adc_dac_enable) begin

    dac_data_L <= signal_from_module_output_port;

    dac_data_R <= signal_from_module_output_port;

    end

    end