Audio CODEC AIC23 vhdl/verilog

Hi EOZF, this is the behavioral sample code. It is working in the software simulation but it is not working in real time application.

coeffs[32] = {,,,}; //32 tap low pass filter coeffs precalculated

x[32];

thread {

input = read input port;

x[0] = input;

output = 0;

for (i=0; i<32; i++)

{

output = output + (x*coeff); //convoluting input with filter coeffs

}

for (i=32; i>0; i--)

{

x[i]=x[i-1]; //need to store 33 samples of input

}

write output to output port;

} //end of thread

In top.v:

always @(clk_in_40M) begin

if(adc_dac_enable) begin

module_input_port <= adc_data_L;

end

end

always @(clk_in_40M) begin

if(adc_dac_enable) begin

dac_data_L <= signal_from_module_output_port;

dac_data_R <= signal_from_module_output_port;

end

end