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User1580871742356367's avatar
User1580871742356367
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Arria 10 HPS DDR4 calibration fail and no emif_usr_clk

Story:

  1. HPS DDR4 calibration failed (discrete, 32bit).
  2. No emif_usr_clk by putting signal tap
  3. PLL locked
  4. both local_cal_success and local_cal_fail are LOW

Questions:

  1. Why there was no emif_usr_clk?
  2. Was Calibration requires SW (boot code/uboot or so)?

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    What leads to you believing there is no emif_usr_clk? Do you not see it coming from the IP in Platform Designer?

    And the first stage bootloader is what runs to initialize and calibrate the external memory, so this is before uboot for Arria 10.

    #iwork4intel

    • User1580871742356367's avatar
      User1580871742356367
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Thank you very much for the reply.

      emif_usr_clk is used as Signal Tap clock and Signal Tap was triggering and waiting for the clock.

    • User1580871742356367's avatar
      User1580871742356367
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      The fitter was failed if using HPS EMIF DDR4 pins (same as A10 SOC Eval Kit) when generating FPGA EMIF example design.

      Alert_n pin is on AG24 and the pins are working for HPS EMIF ( GHRD NAND design)

      Have played with Alert_n settings etc. in Parameters (DQS group, Addr/CMD or auto) and no luck.

      Any suggestions?

      • ybin's avatar
        ybin
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        You need to check whether all the pin location assignment and IP parameter is the same as GHRD .