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User1580871742356367's avatar
User1580871742356367
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5 years ago

Arria 10 HPS DDR4 calibration fail and no emif_usr_clk

Story: HPS DDR4 calibration failed (discrete, 32bit). No emif_usr_clk by putting signal tap PLL locked both local_cal_success and local_cal_fail are LOW Questions: Why there was no emif_us...
User1580871742356367's avatar
User1580871742356367
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

The fitter was failed if using HPS EMIF DDR4 pins (same as A10 SOC Eval Kit) when generating FPGA EMIF example design.

Alert_n pin is on AG24 and the pins are working for HPS EMIF ( GHRD NAND design)

Have played with Alert_n settings etc. in Parameters (DQS group, Addr/CMD or auto) and no luck.

Any suggestions?

ybin's avatar
ybin
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

You need to check whether all the pin location assignment and IP parameter is the same as GHRD .