Forum Discussion

User1580871742356367's avatar
User1580871742356367
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Arria 10 HPS DDR4 calibration fail and no emif_usr_clk

Story: HPS DDR4 calibration failed (discrete, 32bit). No emif_usr_clk by putting signal tap PLL locked both local_cal_success and local_cal_fail are LOW Questions: Why there was no emif_us...
ybin's avatar
ybin
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Agree with sstrell’s opinion. If the PLL is locked, the emif_usr_clk should be OK. Please make sure you tap the correct signal in signaltap. The calibration should act before uboot. As A10 HPS EMIF can be test separately, I think you can use an example design to test EMIF, to see if EMIF can calibrate seperately. Please refer to below link for how to https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf
User1580871742356367's avatar
User1580871742356367
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

The fitter was failed if using HPS EMIF DDR4 pins (same as A10 SOC Eval Kit) when generating FPGA EMIF example design.

Alert_n pin is on AG24 and the pins are working for HPS EMIF ( GHRD NAND design)

Have played with Alert_n settings etc. in Parameters (DQS group, Addr/CMD or auto) and no luck.

Any suggestions?

  • ybin's avatar
    ybin
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    You need to check whether all the pin location assignment and IP parameter is the same as GHRD .

  • ybin's avatar
    ybin
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.