Arria 10 FPGA Development Kit - FMC Connections/Signals

All i want is to connect several LVDS RX links, each consist of 1 Rx clock and 9 RX data lanes to maximum it rate of up to 1,600 b/sec for each lane in DDR mode.

All LVDS signals of each interface off course should to be mapped to same io bank to achieve best timing.

But when i look at Dev Kit schematic i see that some of the signals names on FMC are marked as RX (like the FMCA_LA_RX_P/N9) and some of them are TX (like FMCA_LA_TX_P/N10).

But in the pin list in excel in column named "Dedicated TX/RX Channel" i see no difference between them and looks like all of them can be used as LVDS RX channels/data lanes.

Is it true?

What is the reason for that TX and RX marks in the schematic which so confusing me?