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EHait
New Contributor
New ContributorArria 10 FPGA Development Kit - FMC Connections/Signals
All i want is to connect several LVDS RX links, each consist of 1 Rx clock and 9 RX data lanes to maximum it rate of up to 1,600 b/sec for each lane in DDR mode. All LVDS signals of each interface o...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
The pin connection guidelines is given below link
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-v/pcg-01013.pdf
There is no timing information in the above .
The below document provides more information on EMIF
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
