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EHait
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6 years ago

Arria 10 FPGA Development Kit - FMC Connections/Signals

All i want is to connect several LVDS RX links, each consist of 1 Rx clock and 9 RX data lanes to maximum it rate of up to 1,600 b/sec for each lane in DDR mode. All LVDS signals of each interface o...
EHait's avatar
EHait
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6 years ago

Hi,

Can you be more specific? Can i or can't i use all of them for LVDS RX channels to 1,600 Mb/Sec DDR?

Or at least can you point to the right pin connection guideline file which holds the relevant information? Because i didn't find any timing info related to FMCA_LA_TX_P/N in LVDS RX mode....