New ContributorI am trying to use quartus_sta on a MAX 10 project in Quartus 18.1, but I am getting an error, see error.png It happens when I in the constrainer set the data rate to Double data rate, see constrainer.png. I aperas to me that Intel/Altera have renamed the DDR register but have forgotten to update the quartus_sta script, see ddio.png
Super Contributor
Super ContributorI have never seen an "I/O Timing Constrainer" in Quartus. What is that? A university thing? Can you post the .sdc you're using?
New ContributorIt is part of the Quartus installation, read first page og AN433, start "NIOS II Command Shell". navigate to project directory and run the command
Super ContributorNew ContributorSuper ContributorThe link does not link to any screenshot..
New ContributorSuper ContributorThanks, I was able to launch it.. can attached over your design.qar as well? Otherwise I will have to create it.
New ContributorI have made an example project
Super ContributorThis seems to be a bug, however, Quartus std version are only in maintenance mode. There will be no fix on the bug because in pro edition there are no longer soft LVDS.
What you can do is write the sdc file on your own. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf page 45.
We will file a kdb to let other customer know on this.
Super ContributorI presume you are referring to the -ssc option shown in AN433. I've never even noticed that option before. Perhaps it does not work with MAX 10 devices. I'd recommend following the methodologies in either of these online trainings instead (much easier to understand than that app note):
