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Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
10 months ago
Solved

Altera Max, reset at startup?

Hi there

Im having issue with the startup status on cpld, seems it does not reset itself on bootup or i dont know how to...

So, for instance, a code which alternate output enable signal between latches corresponding 2 srams in ping-pon fashion, ends up as below when first switch on cpld; before i manually press reset button:

U can imagine there is contention since both rams are accessed same time like that...

If i then press reset button (active low), all becomes just perfect as per simulation, rams are alternated:

Is there a need of additional external reset circuitery for cplds?. Above is just example, but i have same issue for other projects too.

Thanks in advance dudes!

BR

Fpga Devkit
  • FvM's avatar
    FvM
    10 months ago
    Hi,
    according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
    Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

    There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

    An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.

9 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    10 months ago

    It's hard to tell without seeing the design, but just like any other logic design, your FPGA design should have a reset state it goes to after device programming.

    • Armando1989's avatar
      Armando1989
      Icon for Occasional Contributor rankOccasional Contributor
      10 months ago

      Hi sstrell

      Attached is design itself. As said, reset is active low. Board has pullup resistor on reset pin with pushbutton. Top module "vga" does invert that logic so reset is high level for the modules on design: "assign _reset=!reset;".

      As said, seems there is no reset at startup itself, so, need to do it by hand pressing button..

      Maybe is better set reset active high on top module and go for a pull down resistor?.

      Thanks in advance!

      BR

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        10 months ago
        Hi,
        according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
        Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

        There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

        An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    Hi Armando,


    May I know if there is any more support/help needed from you for this question?


    Regards,

    Aqid


    • Armando1989's avatar
      Armando1989
      Icon for Occasional Contributor rankOccasional Contributor
      10 months ago
      Hi
      Think is ok by FvM answer, ill check and redesign based on it
      Br
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.