Forum Discussion

Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
10 months ago
Solved

Altera Max, reset at startup?

Hi there Im having issue with the startup status on cpld, seems it does not reset itself on bootup or i dont know how to... So, for instance, a code which alternate output enable signal between lat...
Fpga Devkit
  • FvM's avatar
    FvM
    10 months ago
    Hi,
    according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
    Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

    There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

    An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
10 months ago

It's hard to tell without seeing the design, but just like any other logic design, your FPGA design should have a reset state it goes to after device programming.

  • Armando1989's avatar
    Armando1989
    Icon for Occasional Contributor rankOccasional Contributor
    10 months ago

    Hi sstrell

    Attached is design itself. As said, reset is active low. Board has pullup resistor on reset pin with pushbutton. Top module "vga" does invert that logic so reset is high level for the modules on design: "assign _reset=!reset;".

    As said, seems there is no reset at startup itself, so, need to do it by hand pressing button..

    Maybe is better set reset active high on top module and go for a pull down resistor?.

    Thanks in advance!

    BR

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      10 months ago
      Hi,
      according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
      Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

      There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

      An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.
      • Armando1989's avatar
        Armando1989
        Icon for Occasional Contributor rankOccasional Contributor
        10 months ago
        Hi Fvm nice to hear you again
        Seems as i need some supervisory chip with delay. Ive tried also uncheck power on dont care register content option, wo success... I still need to manually reset after power on for system to behave as expected.
        If any other idea let me know
        Thanks!
        Br