Forum Discussion
Armando1989
Occasional Contributor
Occasional ContributorAltera Max, reset at startup?
Hi there Im having issue with the startup status on cpld, seems it does not reset itself on bootup or i dont know how to... So, for instance, a code which alternate output enable signal between lat...
- Hi,
according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.
There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.
An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.
AqidAyman_Altera
Regular Contributor
Regular ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
