Altera Max, reset at startup?

Hi,
according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.