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Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
3 months ago

Agilex7 CDR not locked to data

When using the F-Tile PMA/FEC Direct PHY Intel FPGA IP for PRBS testing, I am consistently unable to perform PRBS testing in external loopback mode due to the CDR not locked to data. Even when using Intel's IP core example design (FGT NRZ 50G 2PMA lanes RSFEC 528/514), I still cannot proceed with the test. The following images show the CDR status under different loopback modes, but I am unable to pinpoint where the issue lies.

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi,

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi,


    Upon reviewing the Toolkit screenshots, it appears that the CDR successfully achieves lock-to-data mode when using internal serial and parallel loopback configurations. However, when external loopback is used, the CDR fails to lock to data.


    This behavior could be attributed to potential signal integrity issues in the external connection, incorrect pinout, or improper external wiring. Would you mind helping to further investigate these aspects?


    Thank you.



    Best regards,

    Chee Pin


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi,


    Since I do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support.


    If you have a new question, feel free to open a new thread to get the support from Intel experts.


    Otherwise, the community users will continue to help you on this thread.


    Thank you.