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Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
11 months ago

Agilex7 CDR not locked to data

When using the F-Tile PMA/FEC Direct PHY Intel FPGA IP for PRBS testing, I am consistently unable to perform PRBS testing in external loopback mode due to the CDR not locked to data. Even when using ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi,

Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.