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Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
11 months ago

Agilex7 CDR not locked to data

When using the F-Tile PMA/FEC Direct PHY Intel FPGA IP for PRBS testing, I am consistently unable to perform PRBS testing in external loopback mode due to the CDR not locked to data. Even when using ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi,


Upon reviewing the Toolkit screenshots, it appears that the CDR successfully achieves lock-to-data mode when using internal serial and parallel loopback configurations. However, when external loopback is used, the CDR fails to lock to data.


This behavior could be attributed to potential signal integrity issues in the external connection, incorrect pinout, or improper external wiring. Would you mind helping to further investigate these aspects?


Thank you.



Best regards,

Chee Pin