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Xuzeng_'s avatar
Xuzeng_
Icon for New Contributor rankNew Contributor
3 months ago

Agilex7 CDR not locked to data

When using the F-Tile PMA/FEC Direct PHY Intel FPGA IP for PRBS testing, I am consistently unable to perform PRBS testing in external loopback mode due to the CDR not locked to data. Even when using ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi,


Since I do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support.


If you have a new question, feel free to open a new thread to get the support from Intel experts.


Otherwise, the community users will continue to help you on this thread.


Thank you.