Agilex F tile the FGT Xcievers REFCLK

Hi,

LVDS and LVPECL both should be good to use as REFCLK for XCVRS. Can you clarify to me where did you see the XCVRS refclk is driven by AC coupled ,LVDS with 430mv p-p type in the eval board? Is it in the Agilex datasheet?

Regards,

Aqid

Hi Aqid,

Thanks for your reply.

I saw it on the Agillex eval board . its driven with LVDS (at least the note says) with 350mV Swing. (please see previous attachments and attached sheet 38) ,

however the Intel datasheet requires Vrefin diff-AC of 1.2V . please see previous attachments .

I am attaching the evaluation board schematic of the Agillex F- Tile.

please look at sheet 38 for example : REFCLK_156M_QSFPDD_P ,N output of the Silicon labs clock driver.

Thanks

Hi,

Yes, if you follow the evaluation board schematic, you may use LVDS for the F-Tile device.

II may need your clarification on where did you get the screenshot of the 'evaluation si clk gen lvds png.png' file that you have shared?

Regards,

Aqid

Hi Aqid,

Thanks for your reply.

1. So how does it work if the F -Tile Xcievers Refclk can be driven by LVDS , but intel datasheet requires Vdiff AC 1.2V ?

2. screen shot is from the Silicon labs datasheet Si5341A-D10654-GM that is used on the Eval board.

https://www.micro-semiconductor.com/datasheet/7e-SI5341A-C-GM.pdf

Thanks.

Hi,

From what I understand, voltage swing is specified as single-ended mVpp while in the Agilex Datasheet it shows the Vdiff AC as Vpp-diff.

Vpp_diff = 2*Vpp_se

So, based on the LVDS in the Silicon labs datasheet, it shows 430mVpp_se typ. If we calculated according to the formula above, we got 860mVpp-diff which are still in the range of specification stated in Agilex datasheet.

Regards,

Aqid

Hi Aqid, Thanks .

thanks i saw that too . the SI datasheet was somewhat confusing as it seemed to be with respect to the common 1.2V

i assume common mode is diff 1.2V .

so it should interface ok with LVDS driver like the Intel Agillex eval board

Thanks,

still it seems on the low side of the limits . though the SI chip adjusted to higher

Hi,

Yes, what would I say is that you can follow the connection as shown in the Intel Agilex eval board to use LVDS as REFCLK for the XCVRS.

Regards,

Aqid

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