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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

25Gbps transceiver on stratix 10 h-tile

Hello Intel Forums,

I have implemented a 25Gbps transceiver on a Stratix 10 h-tile devkit ( this one ). I am currently sending dummy data out on the TX side, which is looped back into the RX side.

Unfortunately, the RX data has frequent 'glitches' where the data changes in an unexpected way for one clock tick. Meanwhile, the 'data_valid' and 'rx_ready' signals are fixed at '1'.

Here's a signaltap view to show the problem:

I have attached a quartus archive (for Quartus 22.4 Build 94) of my project, if that aids with debugging.

I have also tried this on the MX devkit and see the same behavior.

Board Debug

7 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi SDe_J,


    Can you show clearly where the glitch is? And what is the exact parameters that was affected?


    Best regards,

    Zi Ying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi SDe_J,

    Besides that, can you check that the glitch is at RX parallel data with 1 clock cycle, shap glitch < 1 clock cycle or 1 bit toggled with 1 clock cycle?

    Best regards,

    Zi Ying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi SDe_J,


    Is there any update from your side?


    Best regards,

    Zi Ying


  • SDe_J's avatar
    SDe_J
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello Zi Ying,

    Apologies for the late response.

    I've tried some things without success so far. Note that I've got the 'enchanced PCS/PMA interface width' set to '64' and the 'FPGA fabric/enhanced PCS interface width' set to '67'.

    Here's a screenshot with the glitches highlighed:

    I have tried restricting the `rx_fifo_rd_en` to only be '1' when `rx_fifo_pempty` is `0` to avoid reading from an empty FIFO.

    I have also simulated my target and I do not see the glitches there:

    The simulation shows the data as I expect it.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Sde_J,

    Below are the possible root causes for the glitches:

    1. signal integrity

    2. signaltap sampling issue

    3. potential timing problem at the RX parallel interface

    Solution for each root cause of the glitches:

    1. Use another cable

    2. Try to increase the sampling clock frequency

    3. Check the timing report

    Best regards,

    Zi YIng


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi SDe_J,


    Is there any update from your side? Did your issue has been resolved?


    Best regards,

    Zi Ying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi SDe_J,


    Since no hear any feedback from you, I am now close the case.

    If you have any question after the case closed, please do feel free to submit another issue.


    Best regards,

    Zi Ying