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SDe_J's avatar
SDe_J
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3 years ago

25Gbps transceiver on stratix 10 h-tile

Hello Intel Forums, I have implemented a 25Gbps transceiver on a Stratix 10 h-tile devkit ( this one ). I am currently sending dummy data out on the TX side, which is looped back into the RX side. ...
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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello Zi Ying,

Apologies for the late response.

I've tried some things without success so far. Note that I've got the 'enchanced PCS/PMA interface width' set to '64' and the 'FPGA fabric/enhanced PCS interface width' set to '67'.

Here's a screenshot with the glitches highlighed:

I have tried restricting the `rx_fifo_rd_en` to only be '1' when `rx_fifo_pempty` is `0` to avoid reading from an empty FIFO.

I have also simulated my target and I do not see the glitches there:

The simulation shows the data as I expect it.