关于Cyclone10LP CRC_ERROR报错问题

Hi,

The CRC_ERROR pin cannot be monitored during configuration process. The CRC_ERROR pin will only be enabled after the configuration process is completed. So I would recommend that your system to ignore the CRC_ERROR pin until CONF_DONE pin is high.

Hi John，

​

感谢你的回复与支持，谢谢！

在CONF_DONE拉高之前，我们是可以忽略CRC_ERROR拉高的现象，但是CONF_DONE拉高，CRC_ERROR还有400us的高，这样直接影响我使用这个功能了。想问一下，这个CONF_DONE都拉高了，表示配置完成了，为什么CRC_​ERROR还有老高400us呢？导致我们器件逻辑判断配置异常，需要重新配置器件。请问一下，这个是什么原因导致的呢？有什么解决办法吗？谢谢！

Petteryu

​

​

​

Hi,

After CONF_DONE is high, it will need 3,192 clock cycles for it to fully enter user mode. So if you would like to avoid the miss detection during the device initialization into usermode then I would recommend you to enable the INIT_DONE pin. So once INIT_DONE pin is high the CRC_ERROR pin will work correctly. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf figure 101.

Hi John，

感谢回复，你提的 这个办法可能有用，但是客户产品对安全性要求比较高，能否帮忙分析下CRC_ERROR在配置过程为啥会拉高吗？客户以前有大量使用EP4CE6F17I7N这个料，以前都是判断CRC_ERROR是否拉高判定配置是否有问题。现在10CL016出现这种情况，现在客户想了解的是出现这个现象的原因​？还有与设计有没有关系？客户做的是工业安全产品，对异常现象没有合理的解释，客户不会接受的。您说的方法，可以作为应急方法使用。谢谢！

Hi,

During the configuration mode, CRC_ERROR pin is not enabled yet and this is pin is a dual-purpose pin so it it set to tri-state with weak-pull up. The design will only start to work when it enter usermode. When it is in standby or configuration mode, the all normal pin is in tri-state with weak-pull up. This is to avoid any miss detection by external device.

Hi，

​

CRC_ERROR在双功能引脚，但是没有在dual—purpose引脚里面可以设置tri-state with weak-pull up？只有CRC_ERROR使能引脚？详见附件。

​

还有一个疑问，您说在INIT_DONE置高以后，才进入用户模式，在CONF_DONE拉高以后，还有3192时钟周期后才进入用户模式，理论上按照100MHz，3192*100M=31.92us，10Mhz，3192*10M=319.2us，也就是说，CONF_DONE拉​高，400us应该已经进入用户模式，这个是CRC_ERROR就表明已经配置完成，进入用户模式了又发生了CRC_ERROR报错，原因还是SRAM的吗？或者您说的3192时钟进入完全用户模式，那么这个时钟周期是多少呢？

​

Hi，

​

还有我的理解是CRC_ERROR使能打开，我的理解是在配置过程如果有失败，应该CRC_ERROR应该就会拉高的，我的理解是不需要进入用户模式？不知道我的理解是否正确？谢谢！​

Hi,

Sorry for the confusion on the CRC_ERROR pin. The CRC_ERROR pin is an optional pin where when it is disable then it will be tri-state with weak-pull up. During configuration, if there is any CRC error then the configuration will failed and nStatus will be triggered. The CRC_ERROR pin will only be used to monitor the SEU during usermode. The pin cannot be used during configuration.

The device will need at least 3192 clock cycle for it to enter usermode.

Hi ，

​

请问一下，这个at least 3192 clock cycle 中clock cycle 是哪个时钟？是FPGA外部时钟源的主时钟？还是FPGA内部时钟？时钟周期是多少？请帮忙告知，谢谢！

Hi,

Default it will be related to the internal oscilator except that if your design is using clkuser pin for configuration then user need to make sure to provide additional 3192 clock after CONF_DONE is high.

In other words, if you are using internal clock this number is not important and user will need to monitor the INIT_DONE pin to make sure that it is already in usermode.