Which IP Category is recommended for the Math Square Root function?

Hi Sheng

I have created a sdc file for the design to solve the timing requirements not met issue. The file is attached below for your reference.

Sorry , I don't see the attachment !! I am I missing . sorry for the trouble.

Any feedback for below question

However, I'm having issues with timing and I/O chip placement. Any suggestions?

1. How to calculate / how to find speed grade around for a clock in MHz ?
2. How to determine Maximum combined path delay in ns ?

best regards,

Sriram

Hi Sheng

I am using Intel® Stratix® 10.

I/O Chip is the 1SG280LN2F43E1VG

SDC mean Synopsys Design Constraints

I can successfully compile the design with above attached files.

However, I'm having issues with timing and I/O chip placement. Any suggestions?

1. How to calculate / how to find speed grade around for a clock in MHz ?
2. How to determine Maximum combined path delay in ns ?

Following Critical Warning are reported

• Critical Warning(20615): Use the Reset Release IP in Intel Stratix 10 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.
• Critical Warning(12677): No exact pin location assignment(s) for 34 pins of 34 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
• Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
• Critical Warning(19527): There are 48 unused RX channels and 48 unused TX channels in the design.
• Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
• Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
• Critical Warning(19317): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
• Critical Warning(332148): Timing requirements not met
• Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
• Critical Warning(19317): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
• Critical Warning(19238): Incomplete power management settings for a VID device. As a result, the tool may not generate device bitstream.
• Critical Warning(19239): Missing required setting "SDM PWRMGT SCL output"
• Critical Warning(19239): Missing required setting "SDM PWRMGT SDA output"
  Critical Warning(19239): Missing required setting "PMBus device 0 slave address"

Timing Analysis Error

• Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
• No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
• Timing requirements not met

Thank you

Shriram