Which IP Category is recommended for the Math Square Root function?

Hi Shriram,

I have created a sdc file for the design to solve the timing requirements not met issue. The file is attached below for your reference.

These two critical warnings below can be ignored if you don't intend to use them.

Critical Warning(20615): Use the Reset Release IP in Intel Stratix 10 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.

Critical Warning(19527): There are 48 unused RX channels and 48 unused TX channels in the design.

As for these five critical warnings below may be you have to open a new thread in FPGA, SoC, And CPLD Boards And Kits forum for better guidance and confirmations.

Critical Warning(12677): No exact pin location assignment(s) for 32 pins of 32 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report

Critical Warning(19238): Incomplete power management settings for a VID device. As a result, the tool may not generate device bitstream.

Critical Warning(19239): Missing required setting "SDM PWRMGT SCL output"

Critical Warning(19239): Missing required setting "SDM PWRMGT SDA output"

Critical Warning(19239): Missing required setting "PMBus device 0 slave address"

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.