Which IP Category is recommended for the Math Square Root function?

Hi Shriram,

However, I'm having issues with timing and I/O chip placement. Any suggestions?

Timing issues had been resolved by sdc file. I reattached the file below with new sdc as I further remove the unconstraint paths. As for I/O chip placement you may have to open a new thread in FPGA, SoC, And CPLD Boards And Kits forum for better confirmations.

How to calculate / how to find speed grade around for a clock in MHz ?

The clock frequency can be checked in timing analyzer by report clock. As for speed grade you can refer to this document https://my.mouser.com/datasheet/2/612/s10_datasheet-1652682.pdf Core Performance Specifications section (page 28).

How to determine Maximum combined path delay in ns ?

Can be checked in timing analyzer as well by report timing.

Hope it helps. Thanks.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.