Using Questa Sim instead of IntelFPGA Starter Edition to build simulations

To whom it may concern:

We have a correctly licensed version of Questa Sim V10.7d(64 bit) and are trying to build the dma_afu simulation using Questa Sim instead of the built in Intel FPGA Starter Edition.

So far we have performed the following perquisite steps:

1. Update Environment Variables - We updated the environment variables to point to the licensed version of Questa Sim instead of the Intel Starter Edition.
2. Compile the ModelSim libraries for Questa Sim. The intel documenation references a verilog-library-setup.tcl and a vhdl-library-setup.tcl script file to compile the eda libraries for Questa Sim. Unfortunately the copies found were outdated and did not work. However, using the starter edition library viewer and the supplied files as references a new tcl script file was created which is attached.

#This file contains the commands to create libraries and compile the library file into those libraries.
 
set path_to_quartus /home/common/inteldevstack/intelFPGA_pro/quartus
 
# compiles all libraries
vlib 220model
vmap 220model 220model
vcom -work 220model -2002 -explicit $path_to_quartus/eda/sim_lib/220pack.vhd
vcom -work 220model -2002 -explicit $path_to_quartus/eda/sim_lib/220model.vhd
 
vlib 220model_ver
vmap 220model_ver 220model_ver
vlog -work 220model_ver $path_to_quartus/eda/sim_lib/220model.v
 
vlib lpm
vmap lpm lpm
vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220pack.vhd
vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220model.vhd
 
vlib lpm_ver
vmap lpm_ver lpm_ver
vlog -work lpm_ver $path_to_quartus/eda/sim_lib/220model.v
 
vlib altera
vmap altera altera
vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_europa_support_lib.vhd
vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives_components.vhd
vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives.vhd
vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_standard_functions.vhd
vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_syn_attributes.vhd
 
vlib altera_ver
vmap altera_ver altera_ver
vlog -work altera_ver $path_to_quartus/eda/sim_lib/altera_primitives.v
 
vlib altera_lnsim
vmap altera_lnsim altera_lnsim	
vlog -sv -work altera_lnsim $path_to_quartus/eda/sim_lib/altera_lnsim.sv
vcom -work altera_lnsim -2002 -explicit $path_to_quartus/eda/sim_lib/altera_lnsim_components.vhd
 
vlib altera_lnsim_ver
vmap altera_lnsim_ver altera_lnsim_ver
vlog -sv -work altera_lnsim_ver $path_to_quartus/eda/sim_lib/altera_lnsim.sv
 
vlib altera_mf
vmap altera_mf altera_mf
vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf_components.vhd
vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf.vhd
 
vlib altera_mf_ver
vmap altera_mf_ver altera_mf_ver
vlog -work altera_mf_ver $path_to_quartus/eda/sim_lib/altera_mf.v
 
vlib cyclone10gx
vmap cyclone10gx cyclone10gx
vcom -work cyclone10gx -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_atoms.vhd
vcom -work cyclone10gx -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_components.vhd
 
vlib cyclone10gx_ver
vmap cyclone10gx_ver cyclone10gx_ver
vlog -work cyclone10gx_ver $path_to_quartus/eda/sim_lib/cyclone10gx_atoms.v
 
vlib cyclone10gx_hip
vmap cyclone10gx_hip cyclone10gx_hip
vcom -work cyclone10gx_hip -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_hip_components.vhd
vcom -work cyclone10gx_hip -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_hip_atoms.vhd
 
vlib cyclone10gx_hip_ver
vmap cyclone10gx_hip_ver cyclone10gx_hip_ver
vlog -work cyclone10gx_hip_ver $path_to_quartus/eda/sim_lib/cyclone10gx_hip_atoms.v
 
vlib cyclone10gx_hssi
vmap cyclone10gx_hssi cyclone10gx_hssi
vcom -work cyclone10gx_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_hssi_components.vhd
vcom -work cyclone10gx_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/cyclone10gx_hssi_atoms.vhd
 
vlib cyclone10gx_hssi_ver
vmap cyclone10gx_hssi_ver cyclone10gx_hssi_ver
vlog -work cyclone10gx_hssi_ver $path_to_quartus/eda/sim_lib/cyclone10gx_hssi_atoms.v
 
vlib fourteennm
vmap fourteennm fourteennm
vcom -work fourteennm -2002 -explicit $path_to_quartus/eda/sim_lib/fourteennm_atoms.vhd
vcom -work fourteennm -2002 -explicit $path_to_quartus/eda/sim_lib/fourteennm_components.vhd
 
vlib fourteennm_ver
vmap fourteennm_ver fourteennm_ver
vlog -sv -work fourteennm_ver $path_to_quartus/eda/sim_lib/fourteennm_atoms.sv
 
vlib fourteennm_ct1
vmap fourteennm_ct1 fourteennm_ct1
vcom -work fourteennm_ct1 -2002 -explicit $path_to_quartus/eda/sim_lib/ct1_hip_components.vhd
vcom -work fourteennm_ct1 -2002 -explicit $path_to_quartus/eda/sim_lib/ct1_hip_atoms.vhd
vcom -work fourteennm_ct1 -2002 -explicit $path_to_quartus/eda/sim_lib/ct1_hssi_components.vhd
vcom -work fourteennm_ct1 -2002 -explicit $path_to_quartus/eda/sim_lib/ct1_hssi_atoms.vhd
 
vlib fourteennm_ct1_ver
vmap fourteennm_ct1_ver fourteennm_ct1_ver
vlog -sv -work fourteennm_ct1_ver $path_to_quartus/eda/sim_lib/ct1_hip_atoms.sv
vlog -sv -work fourteennm_ct1_ver $path_to_quartus/eda/sim_lib/ct1_hssi_atoms.sv
 
vlib sgate
vmap sgate sgate
vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate_pack.vhd
vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate.vhd
 
vlib sgate_ver
vmap sgate_ver sgate_ver
vlog -work sgate_ver $path_to_quartus/eda/sim_lib/sgate.v
 
vlib twentynm
vmap twentynm twentynm
vcom -work twentynm -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_atoms.vhd
vcom -work twentynm -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_components.vhd
 
vlib twentynm_ver
vmap twentynm_ver twentynm_ver
vlog -work twentynm_ver $path_to_quartus/eda/sim_lib/twentynm_atoms.v
 
vlib twentynm_hip
vmap twentynm_hip twentynm_hip
vcom -work twentynm_hip -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_hip_components.vhd
vcom -work twentynm_hip -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_hip_atoms.vhd
 
vlib twentynm_hip_ver
vmap twentynm_hip_ver twentynm_hip_ver
vlog -work twentynm_hip_ver $path_to_quartus/eda/sim_lib/twentynm_hip_atoms.v
 
vlib twentynm_hssi
vmap twentynm_hssi twentynm_hssi
vcom -work twentynm_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_hssi_components.vhd
vcom -work twentynm_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/twentynm_hssi_atoms.vhd
 
vlib twentynm_hssi_ver
vmap twentynm_hssi_ver twentynm_hssi_ver
vlog -work twentynm_hssi_ver $path_to_quartus/eda/sim_lib/twentynm_hssi_atoms.v

1. This script file was imported into Questa Sim successfully via loading vsim and using Tools->Tcl->Execute Macro. The libraries were showed loaded/compiled with View->Library

Next we try to build the simulation project:

1. cd to dma_afu directory
2. build sim project

afu_sim_setup --source hw/rtl/filelist.txt build_sim

1. cd build_sim
2. build

make

We get the following error:

** Error (suppressible): (vlog-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
 

This is because the script using to build the project generates the following in the Makefile:

#########################################################################
#                         Questa Build Switches                         #
#########################################################################
## VHDL compile
MENT_VCOM_OPT?=
MENT_VCOM_OPT+= -nologo -work $(WORK)
 
## VLOG compile
# MENT_VLOG_OPT = -64
MENT_VLOG_OPT?=
MENT_VLOG_OPT+= -nologo +librescan -work $(WORK) +define+$(SIMULATOR) -novopt
MENT_VLOG_OPT+= -dpiheader work/dpiheader.h +incdir+$(DUT_INCDIR)+$(WORK)
MENT_VLOG_OPT+= -sv -timescale $(TIMESCALE) -l vlog.log
MENT_VLOG_OPT+= +define+$(ASE_PLATFORM)
ifeq ($(GLS_SIM), 1)
  MENT_VLOG_OPT+= $(GLS_VERILOG_OPT)
endif
 
## VSIM elaboration, and run options
# MENT_VSIM_OPT = -64
MENT_VSIM_OPT?=
MENT_VSIM_OPT+= -c -l run.log -dpioutoftheblue 1 -novopt
MENT_VSIM_OPT+= -sv_lib $(ASE_SHOBJ_NAME) -do $(PWD)/vsim_run.tcl
MENT_VSIM_OPT+= -sv_seed 1234
# -voptargs="+acc"

If the two -novopt lines are edited to remove the -novopt then the make proceeds without issue.

1. Now build simulator

sudo make sim

We get errors like

# ** Error: /home/common/file_dma/hw/rtl/BBB_ccip_avmm/hw/sim/../rtl/ccip_avmm_mmio.sv(89): Module 'scfifo' is not defined.
 

Even though we can bring up vsim and find that specific library in altera_mf_ver

Help would be appreciated on missing steps.