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AUT
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1 year ago

Intel HLS pipeline::lsu won't dispatch more than 8 request

I'm creating a design to load data from HBM using an Avalon memory mapped interface. Due to HBM not supporting typical bursting I need to dispatch as many individual request as possible to get the fu...
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AUT
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1 year ago

Hi @BoonBengT_Altera

I am using HLS 21.1 with a Stratix 10MX developer kit. Sorry if I misspoke, it isn't an example design it is an example of the LSU that HLS generates for my design. The module I posted is from the Verilog that HLS generates. It is generated from a standard mm_master interface with a pipelined lsu transfers specified.