lcl
New Contributor
New ContributorPR on agilex and how to use multi channel dma p tile for pcie?
We have a task to implement PR function，we have find some projects on github，below
https://github.com/intel/fpga-partial-reconfig/tree/master/ref_designs
but my fpga is agilex AGFB023R25A2E3V，I need to change the model of the fpga from s10 to agilex，in this process，pcie IP from s10 to agilex(multi channel dma p tile for pcie),finally we get the .sof file。
After we program the FPGA, access the bar space through mem,it is timeout, and there is no write or read signal on the sinaltap is pulled high.
Can you provide a demo with PR on agilex？
also when we only use multi channel dma p tile for pcie (agilex PCIE IP ),access the bar space through mem,it also is timeout.
thank you，Looking forward to your reply！
