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lcl's avatar
lcl
Icon for New Contributor rankNew Contributor
3 years ago

PR on agilex and how to use multi channel dma p tile for pcie?

We have a task to implement PR function，we have find some projects on github，below https://github.com/intel/fpga-partial-reconfig/tree/master/ref_designs but my fpga is agilex AGFB023R25A2E3V，I n...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi ,


For Partial Reconfig (Agilex) you may refer to AN 953

https://www.intel.com/content/www/us/en/docs/programmable/683849/21-1/partially-reconfiguring-a-design-on.html#:~:text=The%20partial%20reconfiguration%20(PR)%20feature,in%20areas%20outside%20this%20region.


If you need to bring up the system, you may get our golden board design and .sof file from

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/f-series/dev-agf014.html


Hope this helpful.

Regards,

Wei Chuan