Forum Discussion
lcl
New Contributor
New ContributorPR on agilex and how to use multi channel dma p tile for pcie?
We have a task to implement PR function，we have find some projects on github，below
https://github.com/intel/fpga-partial-reconfig/tree/master/ref_designs
but my fpga is agilex AGFB023R25A2E3V，I n...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
