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lcl's avatar
lcl
Icon for New Contributor rankNew Contributor
3 years ago

PR on agilex and how to use multi channel dma p tile for pcie?

We have a task to implement PR function，we have find some projects on github，below https://github.com/intel/fpga-partial-reconfig/tree/master/ref_designs but my fpga is agilex AGFB023R25A2E3V，I n...
lcl's avatar
lcl
Icon for New Contributor rankNew Contributor
3 years ago

hi，

we know AN 953，but we need download bitstream from PICE ，now we access the bar space through wcdma that is busy，so what should we do？

thank you，Looking forward to your reply！

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    What do you mean bar space through wcdma that is busy ?
    can you describe more on that? is there any error message show up ?

    Regards,

    Wincent_Intel