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lkljucaric's avatar
lkljucaric
Icon for New Contributor rankNew Contributor
5 years ago
Solved

oneAPI FPGA Compile Node Errors

I am currently experiencing errors when trying to compile FPGA designs using oneAPI. The errors I'm seeing:

"

Error: Compiler Error, not able to generate hardware

llvm-foreach:
dpcpp: error: fpga compiler command failed with exit code 1 (use -v to see invocation)

"

and further details from quatus_sh_compile.log:

"

This is the PAC OpenCL BSP run.sh script.
Compiling import revision flow...
ERROR: packager check failed with output ''

...

Error (23035): Tcl error:
while executing
"qexec "bash build/run.sh $revision_name""
("default" arm line 9)
invoked from within
"switch $tcl_platform(platform) {
windows {
post_message -type error "Full compiles to generate hardware for the FPGA are available on supported ..."
(file "build/entry.tcl" line 19)
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 981 megabytes
Error: Processing ended: Wed Nov 17 22:32:48 2021
Error: Elapsed time: 00:00:00

"

I assume that something is not configured correctly on some of the fpga_compile nodes. Resubmitting my job sometimes yields successful compilation, but often it fails with this error. I am using the following command to submit to fpga_compile nodes:

"qsub -l walltime=24:00:00 -l nodes=1:fpga_compile:ppn=2 -d . bulid_fpga.sh"

I have used the same command, same shell script, and same source code that have previously compiled successfully.

  • Mickleman's avatar
    Mickleman
    4 years ago

    Hi @lkljucaric

    I had the same problem which was resolved as follows on advice from Intel.

    In the build script add a line at the beginning to ensure that the correct version of Python is used - here is the script I am now using:

    #!/bin/bash
    export PATH=/glob/intel-python/python2/bin/:${PATH}
    source /opt/intel/inteloneapi/setvars.sh > /dev/null 2>&1
    make hw -f Makefile.fpga

    Hope this works for you as well.

    Kind regards

    Marcus

10 Replies

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    5 years ago

    Hi @lkljucaric,

    Thank you for posting in Intel community forum and hope all is well.
    On the Intel DevCloud, there are some cases where the qsub command are executed in the incorrect/corrupted node.


    Hence for that would suggest to use the devcloud_login command and select the appropriate node with OneAPI and proceed with the compilation
    Please do try and let us know that helps.

    Best Wishes
    BB

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    5 years ago

    Hi @lkljucaric,

    Good day, just checking in to see if there is any further doubts in regards to this matter.
    Hope we have clarify your doubts.

    Best Wishes
    BB

    • lkljucaric's avatar
      lkljucaric
      Icon for New Contributor rankNew Contributor
      4 years ago

      I have switched over to using the devcloud_login command to submit my job via batch mode using:

      "devcloud_login -b CO walltime=12:00:00 build_fpga.sh"

      However, I still am seeing the same error generated in quatus_sh_compile.log saying "Full compiles to generate hardware for the FPGA are available on supported ..."

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    4 years ago

    Hi @lkljucaric,

    Thanks for the explanation, can you please let us know which in which node are you facing the issues?
    As well as which example design/user guide which you are following, in order for us to simulate the error and understand further.
    Hope to hear from you soon.

    Best Wishes
    BB

  • lkljucaric's avatar
    lkljucaric
    Icon for New Contributor rankNew Contributor
    4 years ago

    I am not following an example/user guide. I have been working on a project for the past year or so with the DevCloud using oneAPI and FPGAs. I haven't had any issues compiling until recently. Most of the time, the job submission fails with the errors above. However, on occasion, it does find a node where it compiles successfully. The most recent nodes listed in the .oXXXXXXX files that the job was submitted to which resulted in the errors are:

    s001-n057

    s001-n061

    s001-n066

    For reference, my job submission script only contains a "cd" command to the directory where my source files are and the following line for compilation:

    "dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -no-fma -fp-model=precise -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 fpgahw.cpp helper.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw"

    The designs are both software emulated (-DCPU_HOST) and hardware emulated (-DFPGA_EMULATOR) for verification before proceeding to the full compilation steps.

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    4 years ago

    Hi @lkljucaric,

    Appreciate the details explanation on the situation.
    It would seems there might be some node failure and platform inconsistency.
    Apologies for the inconvenient, allow us to look into the mention node and will get back to you.
    Thank you for your patients.

    Best Wishes
    BB

  • Mickleman's avatar
    Mickleman
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi @lkljucaric

    I had the same problem which was resolved as follows on advice from Intel.

    In the build script add a line at the beginning to ensure that the correct version of Python is used - here is the script I am now using:

    #!/bin/bash
    export PATH=/glob/intel-python/python2/bin/:${PATH}
    source /opt/intel/inteloneapi/setvars.sh > /dev/null 2>&1
    make hw -f Makefile.fpga

    Hope this works for you as well.

    Kind regards

    Marcus

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    4 years ago

    Hi @lkljucaric,

    Good day, just following up on the previous clarification.
    By any chances did you managed to try on the solution mention by Marcus?
    Please do let us know if issues still persist.

    Best Wishes
    BB

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    4 years ago

    Hi @lkljucaric,

    Greetings, as we do not receive any further clarification on what is provided, we would assume challenge are resolved. Hence thread will no longer be monitored. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

    Best Wishes
    BB

  • itzmeanjan's avatar
    itzmeanjan
    Icon for New Contributor rankNew Contributor
    4 years ago

    I was facing same issue when I tried compiling some DPC++ FPGA designs on devcloud fpga_compile node today morning & finally I found @Mickleman 's comment above, which resolves the problem. When logged into some fpga_compile node, executing

    export PATH=/glob/intel-python/python2/bin/:${PATH}

    solves interactive compilation related issues.

    Thanks