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Re: oneAPI FPGA Compile Node Errors
I am not following an example/user guide. I have been working on a project for the past year or so with the DevCloud using oneAPI and FPGAs. I haven't had any issues compiling until recently. Most of the time, the job submission fails with the errors above. However, on occasion, it does find a node where it compiles successfully. The most recent nodes listed in the .oXXXXXXX files that the job was submitted to which resulted in the errors are: s001-n057 s001-n061 s001-n066 For reference, my job submission script only contains a "cd" command to the directory where my source files are and the following line for compilation: "dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -no-fma -fp-model=precise -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 fpgahw.cpp helper.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw" The designs are both software emulated (-DCPU_HOST) and hardware emulated (-DFPGA_EMULATOR) for verification before proceeding to the full compilation steps.2.5KViews0likes0CommentsRe: oneAPI FPGA Compile Node Errors
I have switched over to using the devcloud_login command to submit my job via batch mode using: "devcloud_login -b CO walltime=12:00:00 build_fpga.sh" However, I still am seeing the same error generated in quatus_sh_compile.log saying "Full compiles to generate hardware for the FPGA are available on supported ..."2.5KViews0likes0CommentsoneAPI FPGA Compile Node Errors
I am currently experiencing errors when trying to compile FPGA designs using oneAPI. The errors I'm seeing: " Error: Compiler Error, not able to generate hardware llvm-foreach: dpcpp: error: fpga compiler command failed with exit code 1 (use -v to see invocation) " and further details from quatus_sh_compile.log: " This is the PAC OpenCL BSP run.sh script. Compiling import revision flow... ERROR: packager check failed with output '' ... Error (23035): Tcl error: while executing "qexec "bash build/run.sh $revision_name"" ("default" arm line 9) invoked from within "switch $tcl_platform(platform) { windows { post_message -type error "Full compiles to generate hardware for the FPGA are available on supported ..." (file "build/entry.tcl" line 19) Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 981 megabytes Error: Processing ended: Wed Nov 17 22:32:48 2021 Error: Elapsed time: 00:00:00 " I assume that something is not configured correctly on some of the fpga_compile nodes. Resubmitting my job sometimes yields successful compilation, but often it fails with this error. I am using the following command to submit to fpga_compile nodes: "qsub -l walltime=24:00:00 -l nodes=1:fpga_compile:ppn=2 -d . bulid_fpga.sh" I have used the same command, same shell script, and same source code that have previously compiled successfully.Solved2.7KViews0likes10CommentsRe: Invalid Binary for FPGA Stratix 10 Nodes
Investigating this issue further, I am seeing the same error when trying to execute an example vector add program. Is this something to do with changes to USM? Command to compile: dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 vecadd.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw Attached is the source code from dpc++FPGA direct programming examples (vecadd.cpp). Compiled on "nodes=1:fpga_compile:ppn=2" node, executed fpga.hw on "nodes=1:stratix10:ppn=2" node. Passes CPU and FPGA emulation. Full output: Running on device: pac_s10_usm : Intel PAC Platform (pac_ee00000) Caught a SYCL host exception: Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) terminate called after throwing an instance of 'cl::sycl::runtime_error' what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) Aborted1.8KViews0likes0CommentsInvalid Binary for FPGA Stratix 10 Nodes
I recently built new FPGA images for the DPC++ code I have using the new 2021.3 version of the tools. I had previously built the same source code using the 2021.1 version of the tools and executed the designs on Stratix 10 nodes. I noticed that there are new "fast-math" optimizations for FPGAs with the new version of the tools, so I wanted to investigate the changes. The compile/synthesis completes successfully, generates all reports, and provides the executable images. When connected to a node with a Stratix 10 device, I run the executable and get the error: terminate called after throwing an instance of 'cl::sycl::runtime_error' what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) Aborted Is there a disconnect between the compile nodes and the runtime nodes in terms of versioning? I am also wondering if Stratix now requires PACsign like the Arria nodes require too. Either way, there's some disconnect and I cannot find information on what changed. For reference, the command I use to compile is: dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 source.cpp helper.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hwSolved1.9KViews0likes2CommentsRe: OneAPI FPGA C Math Function Support
Hi, I see that according to the oneMKL source (GitHub) that FPGA accelerators are not supported. Like I mentioned previously, the code runs fine when the compile target is the CPU only. I cannot disclose the actual source; however, I have created a simple program that produces the same error. The file mathfunc.cpp contains a similar routine using the exp(), sqrt(), and pow() C math functions. Compile for CPU (throws no error) using: dpcpp -DCPU_HOST mathfunc.cpp -o program Compile for FPGA Emulator using: dpcpp -fintelfpga -DFPGA_EMULATOR mathfunc.cpp -o program Which gives the error: Failed to build device program Error: unimplemented function(s) used: __svml_expf16 is undefined __svml_sqrtf16 is undefined CompilerException Failed to parse IR Error: Compiler Error: OpenCL kernel compile/link FAILED clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation) To execute CPU or FPGA Emulator program: ./program Thank you! Note: I had to zip the source file in order to upload.3.1KViews0likes1CommentOneAPI FPGA C Math Function Support
I have developing designs using the FPGA SDK for OpenCL using both the DevCloud and an on-premise solution. My designs have been fully compiled and executed without issue on either platform. I have been exploring the use of dpcpp/OneAPI for FPGAs for the same designs I have developed with OpenCL. When compiling my dpcpp code for the CPU, the program compiles, executes, and the results are validated. When I target the FPGA emulator (-fintelfpga -DFPGA_EMULATOR), I receive the following compilation error: Failed to build device program Error: unimplemented function(s) used: __svml_expf16 is undefined __svml_sqrtf16_mask is undefined __svml_sqrtf16 is undefined CompilerException Failed to parse IR Error: Compiler Error: OpenCL kernel compile/link FAILED clang++: error: fpga compiler command failed with exit code 1 (use -v to see invocation) My kernel uses the C math functions exp(), sqrt(), and pow(). When removing the exp() and sqrt() functions, the program compiles fine and the FPGA emulation completes successfully. Is there something I am missing to include for the FPGA like oneMKL or is there a missing FPGA implementation for the exp() and sqrt() functions? Any help would be appreciated. All of the OneAPI development is performed on the DevCloud. DPCPP version: Intel(R) oneAPI DPC++ Compiler 2021.1-beta07 (2020.5.0.0604) Target: x86_64-unknown-linux-gnu Thread model: posix InstalledDir: /glob/development-tools/versions/oneapi/beta07/inteloneapi/compiler/latest/linux/bin Thank you!Solved3.2KViews1like7Comments