Modular approach for the NIOS ii processor intigration with main FPGA file

I am currently working on integrating the Nios II processor with the main VHDL file in Quartus Prime. So far, I’ve successfully implemented PWM signal generation by assigning a constant angle using the Nios II processor.

My next goal is to make this system modular, so it can support N angles instead of just one. In my previous implementation, I used a single PIO (Parallel I/O) and assigned a base address to it.

Now, I’d like to know:

• Is it possible to automatically assign addresses for multiple angles (i.e., for multiple PIOs corresponding to each angle)?

• If so, what’s the best approach to manage or generate these addresses dynamically in a modular way?

I’ve also attached the files from my previous implementation for reference.