Forum Discussion

Noman3's avatar
Noman3
Icon for New Contributor rankNew Contributor
8 months ago
Solved

Modular approach for the NIOS ii processor intigration with main FPGA file

I am currently working on integrating the Nios II processor with the main VHDL file in Quartus Prime. So far, I’ve successfully implemented PWM signal generation by assigning a constant angle using t...
Compilation
High-level Design Tools
  • tehjingy_Altera's avatar
    tehjingy_Altera
    6 months ago

    Hi


    One method is you could just add in multiple PIO IP and lock the addresses.

    This can be done by clicking the little lock icon.

    The Addresses of the PIO IP will be fix if you add in additional IPs to the project, this will not mess up the base address of the PIO IPs.


    Regards

    Jingyang, Teh


tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi


Do you have any follow up question on this?


Regards

Jingyang, Teh


Noman3's avatar
Noman3
Icon for New Contributor rankNew Contributor
6 months ago

Many thanks Jingyang of your suport. I have done it by considring the alternating approach.

Regards
Noman