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Mads_From_Denmark's avatar
Mads_From_Denmark
Icon for Occasional Contributor rankOccasional Contributor
1 month ago
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AI Suite - Why does the Sequential IP not take a model argument?

Hello Altera Community

Why does the Sequential IP not take a model argument?

When targeting the Spatial IP, there is an argument where you can input your model, which is an xml file (and a bin file),  exported using OpenVino. Then it will convert these weights and such to .mif files for the FPGA to load. This is easy to understand.

The Sequential IP is a lot harder to understand. I get that the architecture file does all the fpga block related configuration. But I don't understand how it will know which weights to use. Does the Sequential IP only work for the pre defined example graphs?

  • JohnT_Altera's avatar
    JohnT_Altera
    1 month ago

    It will not generate any files need to be included. It will only provide information what is the feature or layers that is not supported due it does not have such features in the IP.

4 Replies

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    The Sequential IP can support multiple model as it is depend on how you implement the features into the IP. So the flow is to run "dla_compiler --network-file model.xml --march my_arch.arch" where it report what is the unsupported layer in the current Sequential IP.

     

    Thanks. 

    • Mads_From_Denmark's avatar
      Mads_From_Denmark
      Icon for Occasional Contributor rankOccasional Contributor

      Okay so the dla compiler can be used to check that the OpenVino model can fit on the Sequential architecture description or it will report a mismatch.

      Will the dla compiler generate any files that need to be manually dragged into the IP repo generated by the dla create ip command? (For example in the spatial IP, the weight mif files will be placed somewhere deep inside the IP repo folder, and then I have to drag them into somewhere the Quartus compiler can find them.) Or are these files loaded into the FPGA after programming, if yes how is this done and what are the relevant files?

      • JohnT_Altera's avatar
        JohnT_Altera
        Icon for Regular Contributor rankRegular Contributor

        It will not generate any files need to be included. It will only provide information what is the feature or layers that is not supported due it does not have such features in the IP.