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Noman3's avatar
Noman3
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Modular approach for the NIOS ii processor intigration with main FPGA file

I am currently working on integrating the Nios II processor with the main VHDL file in Quartus Prime. So far, I’ve successfully implemented PWM signal generation by assigning a constant angle using t...
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  • tehjingy_Altera's avatar
    tehjingy_Altera
    1 year ago

    Hi


    One method is you could just add in multiple PIO IP and lock the addresses.

    This can be done by clicking the little lock icon.

    The Addresses of the PIO IP will be fix if you add in additional IPs to the project, this will not mess up the base address of the PIO IPs.


    Regards

    Jingyang, Teh


tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh